1. Field of the Invention
The present invention relates to methods of forming a semiconductor device and, more particularly, to methods of forming semiconductor devices having field isolation layers.
2. Description of Related Art
In a procedure for forming semiconductor devices, it may be necessary to form field isolation layers. Conventionally, the edge of a field isolation layer is formed to have a substantially right angle. If a gate pattern is formed to reach the edge of the field isolation layer in a subsequent process, then leakage current may be generated at the edge of the field isolation layer.
Specifically, in a semiconductor device such as a NOR flash memory device, a process of forming a field isolation layer may have a direct effect on a profile of a tunnel oxide layer. Thus, program and erase operations and the reliability of the semiconductor device may be affected.
A conventional method of forming a field isolation layer and a floating gate electrode using self-alignment will now be described. A pad oxide pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Using the patterns as etch masks, the semiconductor substrate is patterned to form trenches thereat. After filling the trench with field isolation material, a planarization process is performed to form a filled isolation layer. The mask pattern and the pad oxide pattern are sequentially removed. Generally, the removal of the pad oxide pattern is done using a wet etch. During the wet etch, a boundary portion of the field isolation layer and the pad oxide layer is etched more than the other portions. Accordingly, the edge of the field isolation layer may be dug. A thermal oxidation process is performed on a semiconductor substrate exposed by removing the pad oxide pattern to form a tunnel oxide layer. Oxygen is rarely supplied to the dug portion during the thermal oxidation process, which may prevent smooth formation of a tunnel oxide layer. As a result, the tunnel oxide layer may be thinly formed. A polysilicon layer is stacked to bury spaces between the field isolation layers. A planarization process is performed to form a floating gate electrode. In a subsequent process, an intergate dielectric and a control gate electrode are formed to construct a flash memory device. Thus, the edge of the field isolation layer may be dug and the tunnel oxide layer may be thinly formed in a flash memory device. When the flash memory device is programmed/erased or generally operates, leakage current may be generated at the edge of the field isolation layer, which may decrease the reliability of the semiconductor device.